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In a conference call on Thursday, Intel laid out its mid- to long-term plans for the Itanium Product Family (IPF). With all the hype around Penryn and Nehalem and the ongoing popularity of chatter about Itanium's eventual demise at the hands of 64-bit x86, Intel took a moment to remind the press and analysts that Itanium is still here, still posting double-digit year-over-year growth in revenue and unit shipments, and still looking toward the future. 老域名出售

Indeed, Itanium's future was the focus of the call, in which Intel described its IPF roadmap for the next few product iterations. Here's a summary of what was announced.

The next version of Itanium to hit the streets will be Montevale, which is a tweak of the dual-core Montecito with some additional RAS features.

Following Montevale in 2008 will be the quad-core Tukwila, the next major version of Itanium since Montecito brought the platform into the dual-core realm. Tukwila is a 65nm quad-core part (all four cores are on the same die, so AMD would approve) with an on-die memory controller and support for simultaneous multithreading. Intel claims that Tukwila will offer two times the performance of Montecito at the same TDP.

The major feature that Tukwila will bring to the Itanium line is support for Intel's sorely needed and extremely delayed common systems interconnect (CSI). CSI promises a new socket and bus protocol format that will support either an Itanium chip or a Xeon. Intel will also release chipset hardware that will support either processor on the same motherboard. At last, Xeon and Itanium will be drop-in replacements for one another, a feature that should go a long way in helping with IPF's uptake.

Of course, CSI also offers bandwidth improvements and a host of other features that will finally give Intel a real competitor to AMD's HyperTransport, which by then will be in its 3.0 iteration.

Tukwila's microarchitecture will be essentially the same as that of Montecito, which is itself the same as the Itanium2 processor launched in 2002. IPF's basic microarchitecture won't get a major overhaul until sometime around 2010, when the 32nm Poulson chip launches. Intel was pretty mum on Poulson, not giving too many details.

If Poulson details were scarce, details about its successor, codenamed Kittson, were nonexistent. Intel would only give a codename, with no word on a timeframe, features, or anything else.


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